The present invention relates to a parity checker circuit used in case that data in an integrated circuit are serially transferred.
According to a conventional parity checker circuit of this type, a selection bit for selecting a parity enable bit, an odd or even parity is provided. When a parity is detected, odd or even parity is detected, and if it is coincidence, an error flag is set.
In the above-mentioned conventional parity checker circuit, a problem arises in that its circuit area becomes excessively large, and the size of the chip of its integrated circuit increases.